SiC Device - Chip Reliability: Time Dependent Dielectric Breakdown (TDDB) Testing

Published: 2024-06-12 Views: 次

1. Oxide Breakdown Mechanisms

As the voltage applied across the oxide layer increases, the current through the oxide layer increases due to direct tunneling andFNtunneling. Holes are also generated during this process, and because these holes have almost no mobility in the oxide layer, they cause non-negligible damage to the oxide layer. One explanation for oxide breakdownis that these holes(or electrons) lead to an increase in neutral electron trapsin the oxide layer. When enough of these traps are present, aconduction path composed of traps forms from the gateto the substrate, producing a large current and thermal breakdown.

2 .μ-TDDB:Voltage-Time-Dependent Dielectric Breakdown

A constant voltage is applied to the gate oxide layer at a given temperature, and the leakage current through the gate oxide layer is monitored. When the leakagecurrent exceeds a certain value(for example, 1μA), this time istaken as the dielectric breakdown failure time.

3. J-TDDB:Current-Time-Dependent Dielectric Breakdown

Another way to characterize gate oxide breakdown is the charge-to-breakdown test(Qm). In the charge-to-breakdown test, a constant current is applied to the gate oxide layer, and the voltage across the gate oxide layer is monitored. When the gate oxide layer voltage suddenly drops, weconsider the gate oxide layer to have broken down. This breakdown time is the failure time(t_bd),and Qmis the product of the fixed current andtm. The charge-to-breakdown test(Q_bd)is especially important for nonvolatile memories(nonvolatile memories)such asEEPROMandFlash, becausethe endurance of the tunnel oxide is determined byQ_bd.

4. Failure Models

The commonly used explanatory models forTDDBare the 1/E model and the E model.

1) The hole-induced breakdown model, also known as the 1/E model

When electrons are injected from the polysilicon, some electrons with sufficiently high energy can directly surmount the 3.1eV cathode barrier and be accelerated by the SiO2 electric field to reach the anode. Other lower-energy electrons tunnel into the conduction band of SiO2 via F-N tunneling or tunnel directly to the anode.

If the electric field applied across the gate oxide layer is greater than 5MV/cm, F-N tunneling will dominate, but when the gate oxide thickness is less than 5nm, direct tunneling will dominate. When electrons traverse the oxide layer under a high electric field, they collide with the lattice and are scattered. After reaching the anode, the electrons release energy to the lattice, causing damage to Si-O bonds and generating electron traps and hole traps. On the other hand, the accelerated electrons undergo impact ionization with the lattice at the anode, and the generated holes tunnel back into the oxide layer to form a hole tunneling current. Because the mobility of holes is 2~3 orders of magnitude lower than that of electrons, holes are easily captured by traps. These captured holes in turn generate an electric field in the oxide layer that continuously increases the local current at defect sites, forming positive feedback; traps continue to increase, and when the traps overlap and connect into a conductive path, the oxide layer breaks down. The 1/E model is based on the F-N tunneling current andis applicable to high-field, high-current conditions.

2) The thermochemical breakdown model, also known as the E model

The Emodel assumes that oxide aging and breakdown are thermodynamic processes. The effects of thermal stress and an applied electric field increase the Si-O-Si bond angle from an initial 120° to more than 150°, forming an oxygen vacancy structure and generating weak Si-Si bonds. After the Si-Si bonds break, SP2 hybridization occurs and hole traps appear. Under an enhanced electric field, the breaking of covalent bonds is accelerated, leading to gate oxide breakdown.The Emodel is applicable not only to high-field, high-current conditions but also to low-field, low-current conditions. However, when the gate oxide layer enters the ultra-thin regime, the failure mechanism changes, and the E model cannot well explain the oxide breakdown process.

3) The hydrogen release model, also known as the power-law model

Experimental studies have found that the time-dependent breakdown model of ultrathin oxide layers follows a power-law model.Tunneling electrons release H ions at the SiO2/Si interface at the anode end. Under the applied voltage, the H ions pass through the oxide layer and interact with defects in the oxide layer, causing damage to the oxide layer and eventually forming an ohmic conductive path, resulting in oxide breakdown.

3. Test Methods

The main method for time-dependent effect testing is stress acceleration testing on MOS capacitors. Voltage stress acceleration experiments typically include several test methods such as (1) constant current stress (CCS), (2) constant voltage stress (CVS), (3) ramp voltage stress (RVS), and (4) ramp current stress (RCS). The constant voltage method is generally selected for time-dependent effect testing. The constant voltage method extracts device parameters while ensuring that the electrical stress remains unchanged, and it can vary the temperature while stabilizing the voltage.

a. Chip screening.Measure the basic electrical characteristics of the chip, measure the transfer characteristics and output characteristics of the sample, and at the same time detect the gate leakage current to screen out samples that do not meet the requirements.

b. Set initial conditions. Specify the initial voltage stress and temperature stress for the chip. Usually, three different voltages and different temperature conditions are selected, which facilitates model parameter extraction.

c. Leakage current measurement.During the accelerated stress test, the leakage current of the device needs to be monitored as the criterion for determining whether the device has failed.