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Introduction
Reliability testing is the activity of evaluating whether a product maintains functional reliability throughout its specified lifetime under all expected conditions of use, transportation, or storage. It exposes the product to natural or artificial environmental conditions to evaluate its performance under actual use, transportation, and storage environments, and to analyze and study the degree of influence and mechanisms of environmental factors. By using various environmental test equipment to simulate high temperature, low temperature, high temperature and high humidity, and temperature cycling in climatic environments, the conditions of the product in its service environment are accelerated to verify whether it meets the quality objectives expected in R&D, design, and manufacturing, thereby evaluating the product as a whole to determine its reliability lifetime.
This article summarizes the characteristics and failure criteria of four basic reliability tests for integrated circuits: HCI hot carrier injection effect, TDDB time-dependent dielectric breakdown, EM metal interconnect electromigration, and NBTI negative bias temperature instability.
1. HCI Hot Carrier Injection Effect
Principle: Hot carriers are carriers whose energy exceeds the Fermi level by several kT or more; these carriers are not in thermal equilibrium with the lattice. Hot carriers transfer energy to the lattice through phonon emission, which causes bond breaking at the Si/SiO2 interface, and hot carriers are injected into SiO2 and trapped. Both effects produce oxide charges and interface states, increasing or destabilizing the oxide charge. This affects the mobility of channel carriers and the effective channel potential—this is the hot carrier injection effect.
Test structure: Single MOSFET, with channel length at the characteristic value of the CMOS process, and source, gate, drain, and substrate brought out separately
Test principles: Select devices with minimum geometry, with width selected as needed; determine the worst-case bias stress; select appropriate device parameters to measure the degree of degradation; select an appropriate acceleration model to extrapolate lifetime under normal operating conditions.
Associated parameters: threshold voltage, transconductance, linear-region drain current, saturation-region drain current.
Stress and sequence: Vbs substrate-source voltage, Vbb rated substrate voltage, Vgs gate-source voltage, Vds drain-source voltage.
Test method:
1.Perform initial characteristic measurements.
2. Determine the drain stress voltage (should be less than 90% of the breakdown voltage).
3.Determine the gate stress voltage.
4. Select a new device and begin initial characteristic measurements.
5. Apply stress voltages to gate and drain, run stress cycles, measure and record Gm(max), Ids(sat), Vth(ext) or Vth(ci).
6. Compare results; if not failed, increase stress time and repeat the stress cycle until failure, then stop the experiment and calculate lifetime.
Failure criteria: Ids(sat) degradation of 10%, Vth shift of 50 mV to 100 mV, Gm(max) degradation of 10%
Precautions:
1.Poor probe contact can cause high series resistance or device short circuits, leading to power supply compliance limits and deviations. It must be confirmed that the MOSFET gate has no short-circuit points; a short circuit will cause current to flow through the polysilicon gate, significantly pulling down the voltage.
2.Parameters must be measured as soon as possible after each stress cycle, and the subsequent process performed immediately. This prevents some processes from recovering spatial parameters after the stress bias is removed.
3.When device parameter degradation reaches the stress termination criterion, continuing to apply stress beyond the failure time ensures that if degradation noise is excessive, the data still has a reliable range.4. During testing, it must be ensured that the device under test has not been previously stressed, and the bias used for the test device should not exceed its technical specification or datasheet.
2. TDDB Time-Dependent Dielectric Breakdown
Principle: When enough charge is injected into the oxide layer, breakdown of the oxide dielectric occurs; this breakdown can be induced by applying current or a high electric field across the dielectric layer. At this point, charge injection causes structural changes in the device such as interface states and traps, ultimately creating a low-resistance path through the oxide layer and causing irreversible leakage in the dielectric layer.
TDDB refers to the case where the applied electric field is below the intrinsic breakdown field strength of the dielectric and does not cause intrinsic breakdown of the dielectric, but breakdown still occurs after a period of time. This is because during the application of electrical stress, defects (traps) are generated and accumulate in the dielectric film; when the traps form a conductive path in the dielectric film, shorting the positive and negative electrodes of the dielectric film, the dielectric film fails—this is the TDDB effect.
Test structure: Large-area MOS capacitors (multiple small MOS capacitors connected in parallel may be used)
Test principles: For gate oxide under constant voltage, there are two relationships between electric field and time: the 1/E model or the E model. Since the E model extrapolates a shorter lifetime, the E model is generally used. When the oxide thickness is greater than 2 nm and less than 5 nm, the gate voltage model is used:
Associated parameters: oxide current
Stress: different temperatures (if only one temperature is tested, select the maximum operating temperature of the device), different constant voltages Vgs (use three groups, and the voltage stress should be greater than the device operating voltage).
Test method:
1.Measure leakage current under operating stress
2.After confirming normal, apply temperature and voltage stress
3.Leakage current measurement
4.Leakage current exceeds failure criterion
5.Exceeds the maximum set time
6.Obtain lifetime
Failure criteria: Change in leakage current under stress conditions; when the oxide current increases sharply by 2–10 times or more, irreversible breakdown failure occurs; current change between two adjacent measurement points > 20%.
Precautions:
1.Static electricity has a significant impact on TDDB lifetime; ESD protection must be properly implemented throughout the entire experiment.
2.During high-temperature experiments, the stress voltage should be increased gradually to the set value to prevent instantaneous breakdown.
3.After the stress test, measure the failed samples with the operating voltage; if the current is still large, it is a fatal failure.
4.Regardless of soft or hard breakdown, use the first breakdown as the breakdown time in statistics.
3. EM Electromigration of Metal Interconnects
Principle: A conductor placed in an electric field normally only experiences electron drift, forming a current. If the electric field (current) is large enough to cause directional movement of ions within the conductor, resulting in mass transport, this is called the electromigration EM effect. In integrated circuits, when metal interconnect lines carry currents 10–100 times the normal current density, the EM phenomenon becomes significantly apparent. (Aluminum is typically more susceptible.)
Test structure: Metal strips (with connection holes) of specific width and length fabricated by CMOS process, electrically connected using a Kelvin four-terminal structure.
Test principles: The metal test line should comply with the requirements for electromigration test structures in ASTM document F1259-96, with a uniform cross-sectional area over 95% of the line length.
Associated parameters: R metal interconnect, R via/contact.
Stress: constant temperature, constant current
Test method:
1.Select test structure
2.Initial resistance measurement
3. If normal, determine stress current
4. Determine temperature
5. Perform stress experiment
6. Record resistance change and whether the material fails
7. Stop the experiment upon failure
Failure criteria: Resistance increases by 20% relative to the initial value, considered a failure.
Precautions:
1.During testing, the measurement interval should be less than the failure time.
2.Test samples less than 50%
3.If the sample size is ≤24, then failed samples ≥12 are required
4.Analyze the failure mechanism first.
3. NBTI Negative Bias Temperature Instability
Principle: NBTI is the wear-out mechanism of PMOSFET during channel inversion. Under high temperature and negative bias, the PMOSFET channel inverts, and electrochemical reactions of Si compounds at the Si/SiO2 interface generate donor-type interface states and positive fixed charges, leading to degradation of device parameters. This chemical reaction depends on the gate oxide electric field and channel temperature. Degradation is mainly manifested as a decrease in drive current and transconductance, continuously increasing subthreshold slope, and threshold voltage shift.
Test structure: Single PMOSFET
Test principles: Must be used at the maximum operating temperature, with temperature stabilized within ±2°C; measurement time during stress cycles should be as short as possible.
Associated parameters: Vth, Gm, drive current, subthreshold slope
Stress: Vgs (negative bias), temperature (maximum operating temperature, may be appropriately higher if needed)
Test method:
1.Ramp voltage breakdown test to determine negative gate bias stress, |Vds(max)| < |Vgs| < |1.5Vds(max)|
2.Stabilize at maximum operating temperature, then apply stress after stabilization.
3.Cool to room temperature at the corresponding time points, measure and record Vth
4.Vth shift exceeds failure criterion
5.End experiment
Failure criteria: Threshold voltage shift of 50 mV/100 mV, transconductance degradation reaching 10%.
Precautions:
1. Below 125°C, Vth shift is mostly a coupled effect of NBTI and HCI; the shift at this point is their combined effect. Above 125°C, NBTI is the dominant factor in device degradation.
2.When the device degradation process is too slow and the failure time is very long, time nodes can be set to ensure project progress. If failure has not occurred by the time node, the experiment should be interrupted and mathematical methods used to extrapolate the failure time.
3.When applying stress, source, drain, and substrate are all grounded to avoid excessive FN tunneling effects.
In new-generation semiconductor applications, reliability testing will also change accordingly, which is also due to changes in materials and characteristics. Reliability is always a key metric related to materials, processes, and environment; mastering these elements together with electrical and magnetic conditions or criteria is an irrefutable principle.
