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IWATSU's CS Curve Tracer is a comprehensive instrument commonly used by semiconductor engineers for failure analysis and characteristic curve analysis of discrete semiconductor devices. Today, let's discuss a method for semiconductor failure analysis, or for quickly determining whether a discrete device has failed and rapidly outlining its electrical performance.
The principle is to compare the characteristic curves of the device under test with those of a reference device. Different device types produce distinctly different characteristic curves, and different defects and failure characteristics of the same device also produce different effects on the characteristic curves. Therefore, with experience, one can quickly determine from the characteristic curves what kind of defect is causing the failure signature (short circuit, leakage, or a shift in threshold voltage).
Taking a power MOSFET as an example, we will introduce how to use a CS Curve Tracer to measure a power MOSFET and interpret its curves. This method comes from Hubert Beermann, a senior engineer at Infineon Technologies in Germany.
Since the gate oxide layer is the most sensitive and critical part of a MOS transistor, each measurement can start with the gate, performing gate-source and gate-drain measurements. This can eliminate artifacts that may arise from the use of higher voltage or energy during drain-source testing. If only a quick pass/fail determination is needed, an IGss test can be performed. Since the gate-source and gate-drain can be measured simultaneously, this process is very fast. For failure analysis, however, it is important to observe the differences between each circuit and their distinctive behavioral characteristics. As long as the gate circuit is not shorted, the V-I curve trace can be measured and displayed as a Lissajous figure, then compared and verified against the Lissajous figure of a reference standard device. This method can quickly determine whether the device type matches its marking, and can also indicate whether the device's threshold voltage (Vth) has shifted, and whether leakage or short circuits exist between source and drain.
The Lissajous figure obtained by this method should be measured under a 50Hz sinusoidal AC voltage, reflecting the voltage-current relationship between G-S and G-D of an n-type MOSFET, thereby reflecting the capacitance characteristics that change with voltage.
Measurement Procedure:
1.First, turn on the CS instrument and let it warm up
2.After 30 min, insert the CS-501A fixture into the test box and connect the wiring as shown below
3.After inserting the device into the CS-501A, press the MODE/POLARITY selector in the COLLECTOR SUPPLY section to set the collector supply to AC mode
4.Set ACQUIRE and check whether SINE FREQUENCY is set to 50Hz
5. Press the VOLTS key and the POWER-WATT key to select the appropriate voltage and power limits
6.Set the display parameters: press the MENU key in the DISPLAY section, then press the F1 function key to select the connection method
7.Press the CURSOR key, then press the F2 key to select DOT mode
8.Rotate the VERTICAL knob and the HORIZONTAL knob to select the appropriate voltage and current ranges
9.Turn on the high-voltage output switch and confirm that the safety status bar shows ENABLE. Then turn the VARIABLE knob clockwise to gradually increase the voltage to the target value. The resulting display is the Lissajous figure
Analysis Methods:
1. Differences between G-D and G-S curves when different terminals are left floating
In the figure below, the blue portion is the standard Gate-Drain test curve (Source terminal floating), and the red portion is the standard Gate-Source curve (Drain terminal floating)
Figure 1. Comparison of Lissajous figures with different terminals floating
In the figure, a small marker can be seen in the direction of the arrow; this marks the point where the device begins to conduct. To the right of the marker, the device enters the conducting state, and the two curves overlap, with no significant difference regardless of whether the Drain or Source terminal is floating. To the left of the zero point, the curve represents the body diode in reverse bias when the Gate is at a negative voltage. At this time, the space-charge region increases and the capacitance decreases. The channel is in the off state, and Cgs and Cgd are connected only through Cds; as the capacitance becomes smaller, the current also becomes smaller.
2.Curve comparison between devices of the same type but different specifications
In Figure 2, the red curve represents a device of the same technology type but with a smaller specification, so its capacitance is also smaller, resulting in a lower dynamic current. The lower threshold voltage also causes the current peak to appear at a lower gate voltage.
Figure 2. Curve comparison of devices of the same type with different specifications
3.Comparison of the curve for a drain-source D-S short circuit with the reference curve
Figure 3. Short circuit between DS
Because a short circuit exists between the source and drain of the device, the turn-on of the device channel is affected. Compared with a standard device, the dynamic peak current near the threshold voltage (indicated by the arrow in the figure) is no longer present.
4. Comparison of the curve for leakage between gate and source G-S with the reference curve
Figure 4. Leakage between GS
5.Comparison of the curve for leakage between drain and source D-S with the reference curve
Figure 5. Leakage between DS
In the figure, when leakage exists between drain and source, a 100kΩ resistor is connected in parallel with the capacitance between D-S. In this case, the current in the positive half-cycle near 0V-Vth is larger than that of a standard device, and at the same time the current peak at channel turn-on decreases, as shown in the figure.
6.Threshold voltage Vth shift
Figure 6. Threshold voltage drift
When the chip is subjected to ion contamination, or when the gate oxide layer experiences excessive electric field strength or gate-source overvoltage, the threshold voltage drifts. The figure shows the curve for gate-source overvoltage. The overvoltage causes a tunneling current in the gate oxide layer, but its breakdown energy is insufficient to cause thermal damage. Instead, charged traps appear in the gate oxide layer, causing the VGS(th) peak to shift toward a lower value.
In such cases, the threshold voltage drift can also be reflected by changes in the transfer curve and an increase in IDss.
Summary
This method has a clear, standardized, and efficient workflow. It enables the CS Curve Tracer to quickly determine whether the device type matches its marking, and to accurately identify common failure issues such as threshold voltage shift, source-drain short circuits, and gate-source / source-drain leakage. It provides an intuitive and reliable technical means for quality inspection, troubleshooting, and failure mechanism research of discrete semiconductor devices, significantly improving the efficiency and accuracy of semiconductor failure analysis.
For further questions, feel free to contact us anytime
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Email: yj.yin@jectronic.com
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