Technical Support
Feedback
In recent decades, power semiconductor devices based on silicon carbide (SiC), a newly developed third-generation wide-bandgap power semiconductor material, have attracted much attention due to their excellent performance. Compared with first-generation semiconductor materials silicon (Si) and germanium (Ge) and second-generation semiconductor materials such as gallium arsenide (GaAs), gallium phosphide (GaP), GaAsAl, and GaAsP, SiC has a wider bandgap, stronger high-temperature resistance, higher switching frequency, lower loss, and better stability, and is widely used to replace silicon-based materials or in applications where silicon-based materials are difficult to adapt.
(1) Wider bandgap: The bandgap of SiC is more than 3 times that of Si, enabling it to withstand a higher breakdown field strength (the critical breakdown field strength is more than 10 times that of Si-based devices), so devices can withstand higher peak voltages and output greater power. At the same voltage rating, the drift region of SiC power semiconductor devices can be made thinner, enabling the overall power module size to be smaller and greatly improving the power density of the entire power module. In addition, the on-resistance R on is inversely proportional to the cube of the breakdown field strength; higher breakdown field strength capability means lower on-resistance, reducing conduction loss during device switching and improving power module efficiency.
(2) Higher temperature resistance: It can be widely used in high-temperature operating conditions exceeding 600°C, whereas Si-based devices lose their blocking function at around 600°C because this exceeds their heat resistance. Silicon carbide greatly improves the high-temperature resistance of power devices.
(3) Higher thermal conductivity: The thermal conductivity of SiC is more than 3 times that of Si. High thermal conductivity improves the heat dissipation capability of devices and power modules, reduces the requirements on the cooling system, and helps improve the power density of power modules.
(4) Higher carrier saturation velocity: Compared with Si, SiC has a carrier saturation velocity more than 10 times higher, and the switching frequency of SiC devices is 5–10 times that of Si-based IGBTs, enhancing the high-frequency capability of the devices. SiC devices not only have low on-resistance R on but also low switching losses, improving the high-frequency performance of power modules.
(5) Higher critical displacement capability: Not only is the critical displacement capability of SiC more than twice that of Si, but the radiation stability of SiC devices is 10–100 times higher than that of Si-based devices. SiC-based devices have greater resistance to electromagnetic shock and radiation damage. Suitable for fabricating high-power microwave devices with high-temperature and radiation resistance.
However, most existing packaging technologies still use packaging similar to that of Si-based devices, and many key issues remain to be solved to fully exploit the above performance of silicon carbide.
Due to the high-frequency characteristics of SiC devices, small junction capacitance, low gate charge, and fast switching speed, the rate of change of voltage and current during switching is extremely large. Under extremely high di/dt, parasitic inductance can easily cause voltage overshoot and oscillation, resulting in increased device voltage stress and loss and electromagnetic interference problems。
Regarding the problem of sharply reduced reliability under extreme conditions such as high temperature and severe cold, there is an urgent need to seek connection materials and packaging processes suitable for different operating conditions and to meet the thermal characteristic requirements of different packaging forms.
In response to issues such as internal mutual interference within modules, multi-sided heat dissipation, high-capacity series/parallel connection, and manufacturing cost and difficulty, appropriately reducing the number of thermal interface layers, reducing module volume, and improving power density and multifunctional integration are future trends. The adoption of advanced heat dissipation technologies, pressure sintering processes, integrated power semiconductor chip design, and optimized multi-chip layout plays a key role.
In response to the above problems, experts and teams at home and abroad have developed different packaging technologies to improve module performance, reduce stray parameters, and enhance high-temperature reliability.
Wolfspeed of the United States has developed a high-temperature SiC power module with a junction temperature exceeding 225°C and reduced the parasitic inductance of the power module to 5 nH. The Global Research Center of GE in the United States designed a laminated busbar structure that creates a conduction path overlapping and parallel to the module, reducing loop inductance to 4.5 nH [7]. Germany's Semikron adopted nanosilver sintering and SKiN wiring technology to develop a high-temperature, low-inductance packaging method for SiC power modules. Infineon Technologies AG in Germany has developed high-voltage SiC power modules using press-pack connection technology. Fraunhofer Institute in Germany has developed high-temperature (200°C), low-inductance (≤1 nH) SiC power modules using 3D integration technology. ABB in Switzerland has developed high-power low-inductance SiC power modules using a 3D packaging layout块. ETH in Switzerland adopted a compact design and optimized the power loop to develop a low-inductance SiC power module with parasitic inductance ≤1 nH. Nissan in Japan developed a low-inductance SiC power module based on double-layer direct bonded copper (DBC) packaging, applied to automotive motor controllers.
The excellent characteristics of silicon carbide mentioned above can only be fully realized through reliability design of module packaging layout, selection of packaging materials, parameter optimization, efficient signal transmission, and improvement of packaging processes.
This article focuses on summarizing key technical contents such as low stray parameters under typical packaging structures, the influence of buffer layers in double-sided heat dissipation modules, and power module failure mechanisms, and finally looks ahead to the future development of pressure sintering packaging technology and materials.
With the application demand for third-generation wide-bandgap power semiconductor silicon carbide materials and chips driven by the development of emerging strategic industries, module packaging technology at home and abroad has also developed rapidly. The pursuit of low stray parameters and small-size packaging technology has become a close focus of packaging. Research teams and the semiconductor industry at home and abroad have designed high-performance power modules with various structures, improving the performance of SiC-based controllers.
(1) Traditional packaging: Manufacturers such as Wolfspeed, Rohm, and Semikron mostly continue to use traditional Si-based packaging methods, with lower power levels, metal bonding wires, and relatively large stray inductance.
(2) DBC+PCB hybrid packaging: Cha et al.［16］and Seal et al.［17］By integrating DBC and PCB boards and connecting chips and PCB boards through bonding wires, a DBC+PCB hybrid packaging was innovatively developed. This enables direct control of the commutation loop between PCB layers, shortening the commutation path to reduce parasitic inductance.
(3) SKiN packaging: Semikron in Germany uses nanosilver sintering and SKiN wiring technology, replacing bonding wires with flexible PCB boards to achieve electrical connection between the upper and lower surfaces of the chip. The parasitic inductance of the internal loop of the module is only 1.5 nH［18］。
(4) Planar interconnect packaging: By eliminating metal bonding wires, the current loop is expanded from the planar layout of the DBC board to the interlayer layout of the upper and lower planes of the chip, significantly reducing the loop area and lowering stray inductance parameters. For example, Silicon Power uses direct lead bonding (DLB)［19］, IR's CuClip IGBT［20］and Siemens' SiPLIT technology［21］etc.
(5) Double-sided soldering (sintering) packaging: DBC heat dissipation substrates are soldered on both sides of the power chip to provide heat dissipation channels for the upper and lower surfaces of the chip; or silver sintering technology is used to solder one side of the chip to the DBC and connect the other side to an aluminum sheet. Double-sided heat dissipation can optimize the edge field strength of the substrate, reduce electromagnetic interference (EMI), and reduce the parasitic capacitance to ground at the midpoint of the bridge arm, giving it advantages such as low loss, good thermal performance, and low manufacturing cost. Oak Ridge National Laboratory, CRRC Times Electric, Tianjin University, and CPES can reduce parasitic inductance to 5 nH. At the same time, copper sintering, as a lower-cost chip connection solution, is regarded as a research hotspot in the coming years. Currently, double-sided heat dissipation technology is mainly used in modules inside new energy electric vehicles［2223］。
(6) Press-pack packaging: Press-pack devices rely on pressure contact between the interfaces of each layer of components to achieve electrical and thermal conduction, and are divided into two types: boss type and spring type. Compared with soldered devices, press-pack packaging structure modules have advantages such as high power density, double-sided heat dissipation, low on-state loss, strong impact resistance, failure short-circuit withstand capability, and ease of series connection［24］, and a smaller number of press-pack modules can meet the voltage level and capacity requirements during commutation［25］, but due to sealing and other requirements, LTCC ceramic designs are mostly used, resulting in higher cost, and the press-fit packaging structure is complex. Currently, it is only used in the manufacture of high-voltage modules and has a certain application market. However, there is still a certain gap before practical application in the automotive field.
(7) Three-dimensional (3D) packaging: Tokuyama et al.［26］and Herbsommer et al.［27］The upper bridge arm of the SiC module is stacked directly on the lower bridge arm. Since the SiC module has a vertical structure, the physical length of the commutation loop can be greatly shortened to further reduce the d i/d t. Currently, the biggest advantage of this packaging technology is that the module parasitic inductance can be reduced to below 1 nH. There is also a design that places the terminal with the largest voltage fluctuation in the middle of the three-dimensional sandwich structure, sharply reducing the parasitic capacitance between the terminal and the heat sink［28］, thereby suppressing electromagnetic interference noise［29］。
A cross-sectional view of a typical power module packaging structure is shown in Figure 1.
Figure 1 Cross-sectional view of a typical package structure
Currently, wire bonding is divided into two categories: wire and ribbon. Depending on the metal characteristics, the main materials are Al, Cu, and Au. Aluminum wire is the most basic bonding method; aluminum ribbon has stronger current-carrying capacity and higher strength; Au is relatively less used due to its high cost; and copper ribbon is the trend for the future. Among them, flexible foil, aluminum-coated copper wire, and top DBC copper clip technologies also have certain application markets.
For the 3D package structure of metal wire-bonded modules, dimensionality reduction can greatly simplify the simulation time of the power module structure. The study of converting the 3D structure into a 2D planar structure lays the foundation for research and application of the overall power module, as shown in Figure 2.
Figure 2 Single-sided bonded structure
In this paper, ANSYS Q3D simulation software is used to extract the model's parasitic parameters, with the length of a single metal bonding wireland diameterdas parameters to be optimized, and simulation analysis ofl和don the influence characteristics of parasitic inductance, as shown in Figure 3.
Figure 3 Typical 2D package structure
Thickness of each layer h1h7and edge margin a1a3as optimization parameters, where,a3is the distance from the upper copper of the DBC structure to the edge of the ceramic layer. Because of the requirements of insulation performance, DBC dimples, solder mask, and other processes,a3generally equal to 1 mm. The width of each layer in a conventional typical 2D package structure modulewand thicknesshThe specific dimensions are shown in Table 1.
Table 1 Typical dimensions of power modules
For packaging structures using metal wire bonding, parasitic inductance mainly comes from the bonding wires, and its parasitic inductance［30］can be approximately expressed as
where:lis the bond wire length,l=w1/2+a1；μ0=4 × 107, is the vacuum permeability;dis the diameter of the aluminum bonding wire.
Simulations of bonding wires were carried out with reference to [30], and the results are shown in Figure 4. They were verified to be basically consistent with the data fitting results of equation (1).
Figure 4 Effect of length, diameter, and number of parallel wires on bond wire inductance
Zeng Zheng et al.［31］Research shows that the parasitic capacitance of the chip power loop is mainly determined by the parasitic capacitance of the DBC ceramic layer and can be expressed as
where:ε0=8.85 × 1012 F/m, representing the vacuum permittivity;εr=9, representing Al2O3ceramic relative permittivity. For ceramic AlN and ceramic Si3N4, the relative permittivity is equal to 8.8 and 6.7, respectively.
The simulation results of parasitic parameter distribution are shown in Figure 5, which have been verified to be basically consistent with the data fitting results of equations (1) and (2).
Figure 5 Parasitic parameter distribution
It can also be clearly seen from Figures 4 and 5 that each key variable affects the parasitic parameters. The shorter the bond wire length and the larger the diameter, the smaller the parasitic inductance, with bond wire length having a more significant effect on parasitic inductance; the thicker the ceramic layer and the smaller the area, the smaller the parasitic capacitance, with ceramic layer thickness having a more significant effect on parasitic capacitance.
Reducing the area through which the current flow path passes in the commutation loop of switching devices can reduce stray inductance. By swapping the positions of the freewheeling diode of the upper-bridge SiC MOSFET and the lower-bridge SiC MOSFET, the conduction area of the commutation path is reduced, thereby reducing stray inductance, as shown in Figure 6, with simulation results shown in Figure 7.
Figure 6 Schematic diagram of commutation paths in conventional packaging and stacked packaging
Figure 7 Simulation results of stray inductance for different commutation loops in stacked packaging
Import the package model of the power module into the stray parameter extraction software ANSYS.Q3D, sequentially perform mesh generation and operating condition definition, set the excitation source (Source) and ground (Sink), and add the excitation source to the surface of the power module terminals respectively. Note that multiple excitation sources can be set, but only one ground. Figure 8 shows the mesh generation diagram of the SiC model.
Figure 8 Stray inductance extraction model and mesh generation
Niu Ligang et al.［32］Research shows that the parasitic inductance of a half-bridge power module extracted using ANSYS.Q3D is 20.6 nH, while the actual measured result is 21.23 nH, a difference of 0.63 nH, i.e., a relative error of 3%, proving the accuracy of the simulation extraction method for stray inductance of stacked power modules.
The smaller the parasitic inductance of the metal bond wire, the milder the parasitic oscillation, the smaller the voltage spike during turn-off, the higher the switching speed, and the lower the switching loss; at the same time, the parasitic capacitance of the bond wire should also be as small as possible to suppress the impact of electromagnetic interference.
Lσ和Cσjointly determine the corner frequency of electromagnetic interference (EMI) noisef r：
3 Double-sided cooling technology
The double-sided cooling power module package structure can eliminate metal bond wires, add buffer layers, and optimize the shape, material, and size of the buffer layers, thereby reducing stray inductance, increasing heat dissipation paths, reducing the long-term high-temperature damage to chips in the power module, and improving module service life.
According to the number of buffer layers in the double-sided cooling structure, it is divided into three types: no buffer layer, single buffer layer, and double buffer layer, as shown in Figure 9, among which the no-buffer-layer and double-buffer-layer types are symmetric structures. Buffer layers can take different forms, some of which use metal shims. Reference [33] studied the maximum junction temperature of three module types under chip heating conditions and the thermal stress distribution borne by the metal shim structure.
Figure 9 Structures of different buffer layers
Yang Ning et al.［33］Research found that the thermal stress values of various parts of different metal constructions are shown in Table 2, and the corresponding simulation contours are shown in Figure 10. Among them, due to the structural asymmetry of the single-layer metal buffer layer, its upper and lower stress layers need to be analyzed separately.
Figure 10 Thermal stress simulation contour plots for different buffer layers
Table 2 Thermal stress values of different spacer metal structures (MPa)
It is not difficult to see from the simulation contour plots that: the maximum equivalent thermal stress of the double-sided cooling structure without a metal shim buffer layer is 99 MPa; for the double-sided cooling structure with a single metal shim buffer layer, the maximum equivalent thermal stress of the upper substrate is 109 MPa and that of the lower substrate is 70 MPa. The large difference between the maximum equivalent stress results of the upper and lower substrates is mainly related to the coefficients of thermal expansion of the chip and metal layers and the temperature difference; the maximum equivalent thermal stress of the double metal shim buffer layer is 81 MPa.
Lu Guoquan et al.［34］Research shows that as the thickness of the molybdenum block increases, the stress buffering effect becomes obvious and strain decreases. The maximum von Mises stress of the double-sided interconnected SiC MOSFET chip and the maximum plastic strain of the nanosilver interconnection layer both decrease. At the same time, adding a 1 mm silver shim in the sintered silver interconnection layer between the buffer layer and the upper substrate can further reduce chip stress and interconnection layer strain in the double-sided interconnection structure, improving the thermomechanical reliability of double-sided cooling SiC modules.
Compared with the square buffer layer, the cylindrical buffer layer can effectively eliminate the stress concentration effect of the chip and the nano-silver interconnect layer, and greatly reduce the maximum von Mises stress borne by the SiC chip and the maximum plastic strain of the sintered silver interconnect layer. When the cylindrical buffer layer is used, the plastic strain of the nano-silver layer is reduced by 47.5% compared with that when the square buffer layer is used. This is mainly because the edges of the cylindrical buffer layer transition smoothly, resulting in a more uniform stress distribution, while the edges or sharp corners of the square buffer layer easily cause stress concentration in the chip and the sintered silver interconnect layer, resulting in a sharp increase in local thermal stress.
The double-sided cooling wire-bonded power module is shown in Figure 11. Nakatsu et al.［35］Research shows that the thermal resistance of double-sided cooling power modules is about 50% lower than that of wire-bonded power modules; in addition, they also have excellent electrical performance.
Figure 11 Double-sided cooling wire-bonded power module
Liang et al.［36］Research shows that the switching loss of double-sided cooling power modules is reduced to 10% of that of commercial power modules. Because bond wires cause relatively large parasitic parameter values, bond-wireless modules greatly reduce parasitic parameter values, giving full play to the high-temperature resistance and high-frequency advantages of SiC chips.
Materials in module packaging all have a certain critical thermal stress point; beyond this value, there is a risk of fracture failure. The substrate size of SiC power modules mainly depends on the chip area. The conventional thickness of insulating substrates is 0.03 mm, with a warpage of 3 mil/in. Ceramic materials used as insulating substrates adopt direct bonded copper technology. A stepped edge on the metal layer can effectively reduce stress, and the step height should be half of the copper layer.
The main trend for substrates is to use high-performance materials, reduce the number of layers and interfaces, and maintain electrical, thermal, and mechanical characteristics. Insulated metal substrates (IMS) and IMB substrates are only used for low- and medium-power modules, such as EV/HEV. Mainstream materials are gradually shifting from direct bonded copper (DBC) to active metal brazing (AMB), and high-performance base materials are being adopted. Double-sided cooling structures will promote the use of a second ceramic substrate/lead frame on the top of the module.
Directly cooled substrates, such as pin-fin substrates, reduce the number of thermal interfaces and avoid the use of thermal interface materials (TIM). The integration of substrates and cooling systems, as well as the deployment of cooling module designs and the reduction of the number of thermal interfaces, will be a strong trend, providing new solutions in the coming years. Packaging technology also requires corresponding kits such as ceramic substrates and metal baseplates with high-temperature reliability［3738］。
Silicone and epoxy materials that can withstand the higher operating temperatures of silicon carbide devices are currently under development. To achieve complex and compact module designs in many applications including EV/HEV, silicone is more widely used due to its low cost. The application of epoxy resin materials is still limited by reliability at high temperatures.
The failure mechanisms of power modules mainly focus on electrical, temperature, material, chemical, and other aspects, as shown in Figure 12.
Figure 12 Failure mechanisms of power modules
Common damage to power modules includes overcurrent damage, overheating damage, and overvoltage damage. Overcurrent damage occurs when the current flowing through the power module exceeds the current withstand value; the overcurrent surge causes severe chip heating, exceeding the junction temperature withstand value and thus damaging the chip. Overvoltage damage occurs when the voltage applied between the drain (G) and source (S) of the SiC MOSFETU GSexceeds the withstand voltage value, causing breakdown damage between the device terminals.
To ensure the safe operation of power modules, it is necessary not only to consider the tolerable range of current and voltage of the power module, but also to consider avoiding short circuits in the conduction circuit and shoot-through of the upper and lower bridge arms after the drive signal is applied. Therefore, the safe operation of power modules can be ensured by adding detection and protection circuits and optimizing the control program.
Actual failure phenomena of power modules caused by various reasons［39］are shown in Figures 13 to 19. Among them, short circuits of the freewheeling diodes in the power module and collector-emitter breakdown and burnout are common failure phenomena.
Figure 13 Manifestations of poor welding
Figure 14 Different effect diagrams of ultrasonic wire bonding
Figure 15 Device failure caused by transient overcurrent
Figure 19 Gate failure diagram of the power module
Figure 16 Chip burnout caused by transient overcurrent
Figure 17 Defects in the potting process
Figure 18 Overvoltage breakdown phenomenon of the power module
Uniformly applying thermal grease as a thermal interface material (TIM) on power modules can no longer meet requirements. Metal sintering and other methods are the next research direction. In addition, adding heat sinks, fans, and temperature sensors can effectively prevent overheating. Adding current transformers to detect devices, RC snubber circuits, and optimizing the program drive algorithm can effectively solve overcurrent problems. Bus voltage sampling and comparative protection can effectively solve overvoltage problems.
Traditional material processes based on soldering and wire bonding have unsolvable problems such as low melting points, high-temperature creep failure, wire entanglement, and parasitic parameters. New interconnect materials are developing from soldering toward press-fit and sintering technologies.
Compared with soldered power modules, press-pack modules have the following specific advantages.
(1) Soldering connects the chip and PCB board through wires, which are prone to aging and falling off after multiple power cycles, causing module failure. Moreover, voids in the solder layer increase thermal resistance and reduce reliability. Press-fit uses pressure to press the chip onto the substrate, and current flows directly from the copper plate, improving reliability.
(2) Traditional soldered types are mostly single-sided cooling, while press-fit types are mostly double-sided cooling, which can improve heat dissipation performance and help fully realize device performance.
(3) Bonding wires and solder layers introduce stray parameters; under high-frequency characteristics, voltage and current tend to fluctuate significantly, affecting the chip's series characteristics.
Considering that nanosilver paste has high electrical conductivity, high thermal conductivity, and excellent ductility, and its melting point is significantly higher than that of traditional solders, the relevant research team used nanosilver paste to sinter the chip and the collector molybdenum layer together, successfully developing a silver-sintered press-fit packaged device, demonstrating its certain advantages in the packaging application of press-fit power modules.
Silver sintering packaging can reduce the conduction voltage and on-state losses of press-pack devices, slow the contact wear between the chip and the emitter molybdenum layer, and extend device service life.
At present, sintering packaging technology still has problems that cannot be ignored in its development, and the following feasible solutions are also proposed.
(1) The problems caused by the different coefficients of thermal expansion of silver and the backside material of SiC chips can be improved by adding a metal buffer layer to enhance interconnect performance, but this increases the complexity and cost of the power module packaging process. Replacing the buffer layer with a sintered layer that meets performance and reliability requirements has become a feasible R&D solution.
(2) The electromigration phenomenon of the silver layer is detrimental to the long-term reliable application of power electronic devices. Copper sintering can both reduce electromigration and lower costs, making it a promising alternative for high-temperature die-attach materials.
(3) Optimize the sintering process, innovate sintering schemes, shorten preheating and sintering time, and improve production efficiency; adopt assembly line operation to enhance manufacturability and production design flexibility.
(4) Compared with pressureless sintering, low-pressure sintering offers better reliability and heat dissipation performance. Although some manufacturers have solved the pressure issue, problems such as densification during the sintering process, temperature control of the connection layer, and performance degradation in extreme environments remain to be resolved.
Solving the above problems requires coordinated efforts across the upstream and downstream of the industrial chain, and some problems will be gradually resolved as technology advances. Although current module packaging is almost entirely based on wire bonding, it is expected that in the next 3 to 5 years silver sintering packaging technology will become the mainstream technology for power module interconnection. Because silver ion migration has a negative impact on interconnect structures, and given cost and thermal stress adaptation requirements, transient liquid phase sintering (TLPS), silver-copper sintering, copper sintering technologies, and corresponding solder paste materials, which are similar to silver sintering technology, are also developing rapidly, and some technical bottlenecks are expected to be overcome in the next few years. Die attach, substrate connection, and module-to-heat-sink connection are all potential application areas for sintering technology.
This paper focuses on analyzing and reviewing four key issues in silicon carbide power module packaging: (1) It summarizes low-stray-parameter module packaging forms with various structures and lists and explains the performance advantages of each module; (2) Focusing on typical packaging structures, it analyzes and summarizes the effects of metal bonding wire length, width, and number of parallel wires on parasitic inductance in wire-bonded power modules, the effects of ceramic layer area and height on parasitic capacitance in direct bonded copper (DBC) ceramic substrates, and achievements such as optimizing parasitic parameters using stacked commutation technology; (3) In terms of packaging module heat dissipation, it reviews the effects of buffer layer thickness and shape on heat dissipation and stress deformation in double-sided cooling structures; (4) It compiles common failure maps and solutions for power modules, providing a reference for safe module use. Finally, it discusses the requirements and key issues of advanced silver sintering technology and outlines the development directions of sintering packaging technology and materials.
Source: Harbin University of Science and Technology, Cai Wei, Yang Maotong
